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Porting infrastructure for chapter 1: other modules, byte views, ROM tables, frame-waiting drafts #68

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opened 2026-11-06 09:34:15 +00:00 by Gatchan · 0 comments
Gatchan commented 2026-11-06 09:34:15 +00:00
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Blockers found in #66 (reuse batch 1 ported 12 of ~30):

  • core/game has only field and battle: add menu, btlgfx, world, cutscene, event modules with their bridges (portbridge.py support) and registry rows.
  • Byte views: whole direct page (PushDP/PopDP), BG tilemaps (TfrBG*), HDMA tables (FlipBG1/2) in re/ram_map.toml + accessors.
  • ROM tables: a res accessor for small logic tables read by code (InitNPCSwitches, RestoreParentMap, InitColorMath), per decisions.md 2026-11-03.
  • WRAM port writes (ClearRAM) and divider writes (InitNPCMap) in bridges/platform.
  • draftc.py: drafts for routines that wait for frames (tm_wait_frame, #37), so FadeIn/FadeOut-like routines can be drafted.
  • portbridge.py: routines returning with two index widths (GetTopCharPtr).
    Proof: each item unblocks at least one skipped routine of #66, ported and passing ff6-portcheck.sh.
Blockers found in #66 (reuse batch 1 ported 12 of ~30): - core/game has only field and battle: add menu, btlgfx, world, cutscene, event modules with their bridges (portbridge.py support) and registry rows. - Byte views: whole direct page (PushDP/PopDP), BG tilemaps (TfrBG*), HDMA tables (FlipBG1/2) in re/ram_map.toml + accessors. - ROM tables: a res accessor for small logic tables read by code (InitNPCSwitches, RestoreParentMap, InitColorMath), per decisions.md 2026-11-03. - WRAM port writes (ClearRAM) and divider writes (InitNPCMap) in bridges/platform. - draftc.py: drafts for routines that wait for frames (tm_wait_frame, #37), so FadeIn/FadeOut-like routines can be drafted. - portbridge.py: routines returning with two index widths (GetTopCharPtr). Proof: each item unblocks at least one skipped routine of #66, ported and passing ff6-portcheck.sh.
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